This invention relates to a deflection synchronizing arrangement for a television apparatus.
Display of a television signal picture may be accomplished by repetitively scanning an electron beam over the surface of a picture tube viewing screen. The beam intensity is modulated by video signals to form images on the screen representative of the picture to be displayed. In order to synchronize the scanning of the beam with the display information, the scanning or deflection circuits are synchronized with a synchronizing signal combined with the image information in a composite video signal. As received, the synchronizing signal may contain distortions in the form of electrical noise.
As transmitted, the synchronizing signal pulses recur at a rate which is stable. Because of the presence of noise it has become common practice to obtain synchronization of the horizontal deflection circuit with the horizontal synchronizing signal pulses by the use of an oscillator. The oscillator is controlled by and is included in a phase-lock loop (PLL). The oscillator generates a signal at a frequency that is equal to, for example, a high multiple of the synchronizing signal frequency f.sub.H. Because of the PLL operation, when, for example, one synchronizing pulse is obscured by noise, the rate of the oscillator, nevertheless, remains substantially unchanged, and the deflection circuits continue to receive regular deflection control pulses.
It may be desirable, for purposes of stability of the PLL, to use an oscillator operating at a frequency that is greater than f.sub.H that is followed by a frequency divider that produces from the oscillator signal a horizontal-rate output signal with high stability. The horizontal rate output signal may be locked by the PLL to the average phase of the incoming synchronizing signal.
Such PLL is internal to, for example, an integrated circuit (IC) TA 7777 that is made by Toshiba Co. That IC or other similar integrated current produces, at a corresponding pair of output terminals, a first output signal at the horizontal frequency f.sub.H and a second output signal at a frequency that is 32 times the horizontal frequency f.sub.H, respectively. The first output signal may be used in a television receiver to produce the horizontal rate deflection current.
In the normal operation of a television receiver, a horizontal deflection circuit output stage produces high-voltage retrace pulses. It is customary to derive a high ultor voltage required for operation of a kinescope of the receiver by rectifying and filtering the high-voltage pulses.
The timing of a deflection current in a deflection winding and of the retrace pulses produced by the horizontal deflection circuit output stage may vary in a manner dependent upon loading of the ultor voltage generating circuit. For example, such loading is dependent upon the brightness of the image being displayed on the kinescope. This variation in the timing of the horizontal retrace pulses, disadvantageously, may cause a distortion of the image being displayed.
To prevent the occurrence of a variation in a delay of the deflection current relative to the synchronizing signal, a dual feedback loop arrangement may be used. In such arrangement, a horizontal oscillator generates a signal at, for example, a frequency greater than the horizontal frequency. The oscillator generated signal is divided down in a frequency divider and an output signal near the horizontal frequency is generated. A PLL having a relatively long time constant controls the oscillator to maintain the output signal in frequency and phase synchronism with horizontal synchronizing signals. The frequency divider may be included in the PLL. In order to compensate for load-dependent variations in the delay of the horizontal deflection circuit output stage, a phase-control loop circuit (PCL) may be used. The PCL includes a phase detector, a first input terminal of which is coupled to an output of the PLL and a second input terminal of which is coupled to the deflection circuit output stage for responding to the retrace pulses. The phase detector produces a phase difference indicative signal from the signals at the first and second input terminals. A loop filter is coupled to an output of the phase detector to form a control signal. A controllable phase shifter is responsive to the control signal that is generated by the loop filter for producing horizontal-rate drive pulses at a variable delay which makes the retrace pulses synchronous with the output signal of the PLL even when variations of beam current loading occur. The PCL may require for its internal operation timing signals at various multiple frequencies of the horizontal frequency that are at corresponding predetermined constant phases relative to the horizontal rate output signal of the PLL. Each of such timing signals may be generated from, for example, the second output signal that is generated in the PLL that is at a high multiple, or 32 of the horizontal frequency.
The PCL may be located internally to a second IC that is separate from the first IC that generates the second output signal. An indicated before, the second output signal is at the fundamental frequency that is equal to 32Xf.sub.H. In addition to the signal component at the fundamental frequency of 32Xf.sub.H, the second output signal may include undesirable high order harmonics that cause the waveform of the second output signal to deviate from an ideal square-wave. Such undesirable harmonics may, disadvantageously, cause perturbation in synchronizing the PCL of the second IC.
It may be desirable to couple the 32Xf.sub.H signal from the first IC to the second IC via a coupling arrangement such that the high order harmonics from the PLL are prevented from adversely affecting the operation of the PCL in the second IC.
When, for example, a user selects a new television channel for viewing, the second output signal at 32Xf.sub.H generated by the PLL in the first IC may be significantly disturbed during a transition interval as a result of a loss of a horizontal synchronizing signal. Such disturbance may, disadvantageously, cause a temporary loss of a drive signal generated by the PCL, causing a temporary shutdown in a deflection circuit output stage. This is so because when the drive signal generated by the PCL in the second IC is lost the output stage does not produce the ultor voltage and other energizing voltages that are required for operating the television receiver. Moreover, if the drive signal is erroneously generated at a frequency that is substantially lower than the nominal frequency f.sub.H, the ultor voltage may increase to such a level that causes a high voltage protection circuit to initiate a complete shutdown. Therefore, it may be desirable to provide the PCL in the second IC, during such disturbances, with a signal at, approximately, the frequency 32Xf.sub.H, should the second output signal be significantly disturbed.